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Single Cycle Store in a Single Ported Tag Implementation Disclosure Number: IPCOM000117879D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31

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Eisen, L Kuttanna, B Mallick, S Patel, R [+details]


Disclosed is a scheme where the access to the cache for a store request is split up into the tag access and the cache array access which enables pipelining of back to back stores. The mechanism allows to execute stores in fully pipelined fashion with a clock latency of one store per cycle.