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Cascade Digital Phase Aligner Disclosure Number: IPCOM000117919D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31

Publishing Venue


Related People

Casal, H Li, HH Nguyen, T Thoma, NG [+details]


Disclosed is a method of minimizing global system clock skew by utilizing multiple levels of the Digital Phase Aligner (DPA). This scheme makes the clock arrival times the same even though there may be unequal electrical path lengths from one FRU to another.