Browse Prior Art Database

Cascade Digital Phase Aligner

IP.com Disclosure Number: IPCOM000117919D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31

Publishing Venue

IBM

Related People

Authors:
Casal, H Li, HH Nguyen, T Thoma, NG [+details]

Abstract

Disclosed is a method of minimizing global system clock skew by utilizing multiple levels of the Digital Phase Aligner (DPA). This scheme makes the clock arrival times the same even though there may be unequal electrical path lengths from one FRU to another.