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Disclosed is a high speed interface method between a read/write channel and a Hard Disk Controller (HDC) and a Micro Processor Unit (MPU).
English (United States)
This text was extracted from an ASCII text file.
100% of the total text.
Sharing Data Bus and Channel Control Register
a high speed interface method between a read/write
channel and a Hard Disk Controller (HDC) and a Micro Processor Unit
This interface comprises the following features:
Customer data bus and channel control register are shared inthe
Channel control register are read or written in parallel, in
sequence of address and data.
Channel control register is modified asynchronously by the
channel read reference clock.
The Figure shows an example algorithm of this interface.
with this method, the channel register transfer
time is minimized to three channel register clocks, for example.
This high speed channel register transfer method is useful especially
in Partial Response Maximum Likelihood (PRML) channel application
which uses a lot of register.