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Pseudo Two-Bit Multiplier for Decreased Delay and Circuit Size Disclosure Number: IPCOM000118051D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31

Publishing Venue


Related People

Imming, KC Kalla, RN [+details]


Disclosed is a hardware binary multiplier for reduced circuit area and delay that achieves two-bit non-overlapping add-shift performance 75% of the time.