Self-Resetting Control Circuits for Dynamic Complementary Metal Oxide Semiconductor 64-bit Parallel Adder
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Chappell, TI: AUTHOR [+2]
Disclosed is a self-resetting circuit technique which provides the solutions for precision control of reset timing, evaluation and resetting pulse-width adjustment, cycle time improvement and conduction collision problems.
Self-Resetting Control Circuits for Dynamic Complementary
Semiconductor 64-bit Parallel Adder
a self-resetting circuit technique which provides
the solutions for precision control of reset timing, evaluation and
resetting pulse-width adjustment, cycle time improvement and
conduction collision problems.
carry look-ahead 64-bit parallel SRCMOS adder is
designed. The adder core consists of of several basic evaluation
macros and self-resetting control macros. The basic evaluation
macros of the adder core consists of a Propagate/Generate/Zero (PGZ)
generator circuit, a PGZ buffer circuit, a PGZ merge circuit, a
carry generator circuit, a carry buffer circuit, a carry merge
circuit, a half-sum circuit and full-sum circuits. The
self-resetting control circuit macros of adder core will be
described later. Each of these macros consists of a trigger
circuit, inhibit-reset block, hold-reset-state block and a reset
timing chain circuit. All circuits are design with enhanced
adder forward evaluation block is partitioned into
8 rows of evaluation logic (Row1 to Row8) and 2 rows of reset-trigger
logic (RR and RR8 shared with Row8). The first seven rows of adder,
with the exception of the SUM8, are reset with timing chain generated
from the self-resetting control RESET_I block. A simplified
illustration of the circuit showing the interaction between the
forward and reset paths is shown in Fig. 1. The uppermost chain of
circuits represent the forward circuit performing the logic. To see
the labels, only four of the seven rows of circuitry is shown here.
For simplicity, the pulldown trees are represented by a single
transistor. An input pulse width is shown to arrive into the input.
Below the forward path is the timing chain of inverters forming the
reset path. The trigger devices which pull down the "done" line are
part of the forward path marco, but are shown in the reset loop to
illustrate the transistors which initiate reset, reset of the reset
circuitry, and pulsewidth of the reset pulse. A conductance diagram
for each rows of the forward path and reset timing can be derived by
using the reset Spreadsheet representation of the design plan. In
order to allow good margin for pulse coalescence, it is desirable to
have shorter pulsewidth at the macro boundaries. Thus, separate
reset circuity (RSUM) is used to reset the SUM8 blocks.
Fig. 1 also
shows how the Power On Reset and Evaluate functions
are added to the basic circuit. The Evaluate is implemented by ANDed
with a complement of the "evaluate" signal to interrupt the reset.
This block is defined as "Inhibit Reset" block. If not inhibited by