64Bit PowerPC Common Hardware Reference Platform Systems with Modified 32Bit PowerPC Common Hardware Reference Platform Open Firmware
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Disclosed is a specific 64-bit PowerPC* Common Hardware Reference Platform, CHRP**, Open Firmware implementation. This implementation derives from a 32-bit PowerPC CHRP Open Firmware implementation and provides 64-bit physical address support, as well as 32-bit open firmware device driver compatibility.
64Bit PowerPC Common Hardware Reference Platform Systems
32Bit PowerPC Common Hardware Reference Platform Open Firmware
a specific 64-bit PowerPC* Common Hardware
Reference Platform, CHRP**, Open Firmware implementation. This
implementation derives from a 32-bit PowerPC CHRP Open Firmware
implementation and provides 64-bit physical address support, as well
as 32-bit open firmware device driver compatibility.
To derive the
specific 64-bit PowerPC CHRP open firmware
implementation to run on a 64-bit PowerPC CHRP compliant system which
may have either 32-bit or 64-bit physical address, open firmware will
be provided from system initialization code with two items:
o A variable indicating the address width of the system. This
variable is FALSE (0) if the system is only capable with
32-bit address. Otherwise, the variable is TRUE (-1) if the
system is capable with physical address which is more than
32 bits. Let's name this variable 64-bit-addr?.
o A variable indicating the size of system memory in Mega-Byte
(MB) starting at physical address 4 Giga-Byte (GB), i.e.,
0x100000000. This variable must always be 0 for 32-bit
physical address systems. But it can be 0 if there is no
system memory starting at 4GB in a system which has physical
address that is more than 32 bits.
virtual memory management code of the 32-bit PowerPC
open firmware will have to be replaced by the virtual memory
management code which handles the 64-bit PowerPC virtual address
translation hardware specified by the PowerPC architecture.
Specifically, the changes are:
1. Set up the 64-bit PowerPC processor to operate in 32-bit
mode. Even the processor is in 32-bit mode, Data residing
above 4GB can still be accessible through 32-bit virtual
address by means of virtual address translation.
2. Provide the Data Storage Interrupt (DSI) and the Instruction
Storage Interrupt (ISI) handlers to handle page faults
during data accesses and instruction fetches.
3. Modify the structures to describe how a 32-bit virtual
address range is translated into a 64-bit physical address
range. These structures are used by the open firmware code
to establish address translation and used during a page-fault
By now, the
open firmware core will be changed. In
node of the device tree, the following changes are needed:
o #address-cells and #size-cells properties of the root
node are both set to 1 if 64-bit-addr? is FALSE, and
to 2 if 64-bit-addr? is TRUE.
o The ENCODE-UNIT method will encode one 32-bit hex number
into an 8-byte ASCII hexadecimal string when 64-bit-addr? is
FALSE. It will encode two 32-bi...