Browse Prior Art Database

604 Pin Grid Array Socket Definition Disclosure Number: IPCOM000118405D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 48K

Publishing Venue


Related People

Dixon, RC: AUTHOR [+1]


Disclosed is a technique to enable multi-processors for a single Pin Grid Array (PGA) socket.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 87% of the total text.

604 Pin Grid Array Socket Definition

      Disclosed is a technique to enable multi-processors for a
single Pin Grid Array (PGA) socket.

      Using normal pin assignments, PGA sockets allow only single CPU
by definition of the pin allocation of the CPU manufacturer.  Pins
not allocated are normally reserved or not connected.  By utilizing
"not connected" pins on the CPU, extra signals are routed to the PGA
socket enabling Multi-Processor (MP) operation.

      The addition of extra signals in the bus arbitration, interrupt
and processor environment group allows for two CPU's to be supported
by a single PGA socket.

      The implementation of the MP may either be via a MP circuit
board, accommodating two CPU's or via Multi-Chip Module (MCM)
technology.  In addition to MP implementations, other CPU bus, bus
masters may share the PGA socket with a single CPU.  Examples of
other bus masters would be L2 caches and auxiliary special purpose

The signals enabling an MP solution are as follows:
  BR*      PIN  A17    BUS REQUEST  CPU 1.
  BG*      PIN   J5    BUS GRANT  CPU 1.
  DBG*     PIN   K1    DATA BUS GRANT 1.
  BR2*     PIN   E8    BUS REQUEST  CPU 2.
  BG2*     PIN  E13    BUS GRANT  CPU 2.
  DBG2*    PIN  R15    DATA BUS GRANT CPU 2.
  INT*     PIN  E14    INTERRUPT  CPU 1.