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Method for combining gate level and behavioral simulation models of a hard core. Disclosure Number: IPCOM000119115D
Original Publication Date: 2005-Apr-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 1 page(s) / 21K

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Method for combining multiple simulation models of a hard core.

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Method for combining gate level and behavioral simulation models of a hard core .

Disclosed is a method for combining a plurality of simulation
models of a given hard core, where each model provides some
subset of the overall functionality of the core, and a state
machine is used to determine which of the implementations will
drive the output pins based on the mode of operation.

Above is a diagram of a sample implementation, combining a
gate-level and a behavioral simulation model of a core. A top
level module is created which instantiates both implementations
of the core. The inputs to both core models are driven from the
inputs to the top level module. The outputs of the two modules
feed multiplexers for which the mux select is driven from a mode
selector module. The mode selector module monitors the top level
module inputs and determines which of the implementation's
outputs are appropriate given the current mode of operation.

This structure could be extended to an arbitrary number of core
implementations. Additionally, different output pins could be
driven from different implementations at the same time.


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