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Productivity Concepts for Cross-Mapped Layout Browsing Disclosure Number: IPCOM000119116D
Original Publication Date: 2005-Apr-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 20K

Publishing Venue



The ability to easily navigate the physical layout and correlate shapes to logical entities is essential for diagnostics activities in a semiconductor manufacturing environment. This work addresses the productivity concepts and functionalities required for a cross-mapped layout browser.

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Productivity Concepts for Cross -Mapped Layout Browsing


Disclosed is a cross-mapped layout browser suitable for VLSI diagnostics activities in a semiconductor manufacturing environment. Semiconductor devices are designed using heterogeneous electronic design automation (EDA) tools, and their manufacturing process includes many complex steps. The yield learning process, a key to profitability and customer satisfaction, requires the ability to easily browse the mask data and to correlate physical features, e.g., a shape at metal level M1, to design schematic features, e.g., nets, instances, and cells. Many layout browsers are available in industry; most of them are not suitable for the task because their user interfaces lack many diagnostics and productivity concepts, making their use cumbersome and time consuming. Moreover, they rely on in-core data structures requiring excessive loading time and memory requirements. The following summarizes the browser's features and functionalities:

Deployment: the application is deployed as stand-alone and in a web environment where users launch the application using pointers on web pages.

Authentication: the application provides a flexible authentication scheme; the system administrator can authorize each user to open a selected subset of designs.

Cell browsing: the user can open and browse multiple design cells at the same time without restriction on the number of simultaneous open instances of a specific cell.

Display Control: design shapes can be displayed as is, or rotated and/or mirrored according to user selection. The user has the choice of what design levels to display and in which order. Along with the normal design levels, an additional level representing the boundaries of cell instances is provided. Moreover, for hierarchical designs, the user can specify what hierarchy depth range to display. For example, it is possible to display only the shapes of the prime cell or the shapes in instances two-level deep in the hierarchy. As it is difficult to read rotated and/or mirrored design text annotations, the user can instruct the browser to display them always straight along with a mark designating the text origin. The browser displays a thumbnail containing a rough hierarchical view of full chip in which the current view port is outlined. Besides the usual browsing functions like zooming and panning, clicking on the thumbnail causes the browser view port to pan to the corresponding location. A history navigator allows the user to play back and forth his previous view ports. To prevent lengthy redraws, the user has the option to specify the minimum shape size...