BICMOS RAM Cell
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Kemerer, DW: AUTHOR [+2]
An array cell is described for a random-access memory (RAM) providing the density of CMOS and performance of a bipolar emitter follower.
BICMOS RAM Cell
An array cell
is described for a random-access memory
(RAM) providing the density of CMOS and performance of a bipolar
array cell allows a high performance
emitter-follower to be integrated into a high density memory array.
The cell, shown in Fig. 1, requires a clocked RAM architecture with
bit lines (BLs) pre-charged low. Depending on the polarity of cell
data, the bit line will either remain low or be pulled high during an
access. Also, R1 may be a very small NFET with its gate held high.
The cross-coupled inverters, T1 through T4, comprise the storage
latch and are known. Advantages may be gained if T3 and T4 are
replaced by high resistance loads when resistors are available in the
fabrication process. The write port (Tw) is also known and the NFET
shown may be replaced with a PFET. If these replacements are made
(resistors replacing T3, T4, and PFET replacing NFET), all elements
may be built in the n-well with the following advantages:
1. No n+ - p+ diffusion space is required.
2. Better soft-error protection is realized.
3. The array metal wiring may be reduced by pulling
Vdd out of the subcollector utilizing
Fig. 1, when the stored cell data holds the gate
of T5 low and Read WL becomes active (low), a substantial current
surges out of Vdd, through T5 and T6 and into the base of Q1, pulling
Read BL high. Because latch T1 - T4 only control a g...