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# Dynamic Sized Operand Single-Cycle Shift/Rotate Unit

IP.com Disclosure Number: IPCOM000120137D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 56K

IBM

## Related People

Carnevale, MJ: AUTHOR [+3]

## Abstract

A single-cycle shift/rotate unit is described. The shift/rotate operation is performed in one cycle, and the type of operation and the size of the operand is variable.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 79% of the total text.

Dynamic Sized Operand Single-Cycle Shift/Rotate Unit

A single-cycle shift/rotate unit is described.  The
shift/rotate operation is performed in one cycle, and the type of
operation and the size of the operand is variable.

The shift/rotate unit accomplishes single cycle shifts/rotates
by implementing 3 levels of busing as shown in Fig. 1.  For each
level of the unit, 2 signals are used to control the amount of
shifting/rotating done.  For example, on the first level of the unit,
Shift1 and Shift2 control the shifting.  If neither signal is active,
no shift/ rotate is performed.  If Shift1 is active and Shift2 is
not, a shift/ rotate of 1 bit is performed.  If Shift2 is active and
Shift1 is not, a shift/rotate of 2 bits is performed.  If Shift1 and
Shift2 are active, a shift/rotate of 3 bits is performed.  Similarly,
for the second level, shifts/rotates of 0, 4, 8, or 12 bits can be
performed, and, for the third level, shifts/rotates of 0, 16, 32, or
48 bits can be performed.  The overall maximum shift/rotate amount is
63 bits.

Operands to be shifted/rotated can be 8, 16, or 32 bits long.
Size and data type information are provided to the unit via encoded
inputs, and the hardware multiplexes the right inputs to the 3
shifter levels.

To simplify the logic, if an 8- or 16-bit operand is to be
rotated without the carry flag, the operand is replicated to fill the
32- bit input bus.  For example, a byte operand is presented to t...