Efficient Dual-Port First-In, First-Out Buffer With an Overrun And Underrun Detection Scheme
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Johnson, RD: AUTHOR [+5]
This article describes a scheme for detecting the overrun and underrun conditions in a communication network while guaranteeing the data integrity of the first-in, first-out (FIFO) buffer.
Efficient Dual-Port First-In, First-Out Buffer With an
Underrun Detection Scheme
describes a scheme for detecting the overrun
and underrun conditions in a communication network while guaranteeing
the data integrity of the first-in, first-out (FIFO) buffer.
Layer 2 and
layer 3 of a communication network can exchange
information by sending protocol messages to each other. The layer 2
processing is done by an intelligent I/O card connected on a time
division multiplexing (TDM) bus to the host communications broadcast
exchange (CBX). Special FIFO buffers are used to efficiently
exchange data across this bus. The detection and handling of overrun
and underrun conditions can be a problem since it can occur from
either the host side or the card side of the FIFO.
buffer disclosed herein is shown in block diagram in
the drawing with associated pointers and individual wrap-around bit
indicators. It consists of the following components:
1. A block of readable/writeable buffer.
2. An input (write) pointer.
3. An output (read) pointer.
4. Control logic for the Read/Write operations (not
5. Wrap-around bit indicator for each pointer.
buffer is fixed in size and addressed sequentially.
When the bottom of the buffer is reached by the maximum count of the
pointer, the next operation will set the pointer to zero address and
start back on the beginning of the buffer (i.e., wrap-around).
condition occurs when a FIFO location is overwritten
before it is read. The underrun condition occurs when a FIFO
location is read before valid data has been written into it. The
FIFO design must include not only error detection, but also blocking
of the wrong operation so that FIFO data integrity is maintained.
specific application, the host CBX will send a sequence
of messages through the TDM bus and s...