Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
A very large-scale integrated circuit (VLSI) architecture is described which is optimized for component testing and for multi-component interconnect testing.
large-scale integrated circuit (VLSI) architecture
is described which is optimized for component testing and for
multi-component interconnect testing.
the figure, component input/outputs (I/Os) are
divided into groups as follows:
1. Test Access Port (TAP) inputs and output
2. TAP level-sensitive scan design (LSSD) Test
3. System LSSD Test Function I/Os
4. Other Test-only I/Os
5. LSSD Scan-only I/Os
6. Combined System Data and LSSD Scan I/Os
7. Other (System Data) I/Os
provides signals to and from TAP logic, thereby
allowing operation in conformance to IEEE standard 1149.1.
1149.1 does not conform to LSSD clocking rules,
group 2 inputs allow the TAP logic to be operated in conformance with
LSSD rules. Because these signals affect operation of TAP logic, the
IEEE standard does not allow them to be used during normal system
operation; only Tap interface signals may be used to control TAP
logic. The LSSD Test Function Inputs must be held (to 0 or 1) for
consists of those signals that are Test Function I/Os
for LSSD testing but also are used for normal system operation. An
LSSD clock input might be used as a system clock, for example. Since
these I/Os are used for system operation, the IEEE standard...