Structure and Process for Self Aligned Shallow Source/ Drain Extensions For CMOS Technology

Structure and Process for Self Aligned Shallow Source/ Drain Extensions
For CMOS Technology

      Disclosed is a process for forming self-aligned, low
resistivity source/drain extensions for advanced CMOS technology.
The extensions are formed using a diffusion technique which forms
shallow junctions not obtainable using ion implantation.  Junctions
formed by this diffusion are highly doped and do not require anneals
to remove implantation damage.

      Doped glasses were used to create sidewalls on polysilicon gate
electrodes of FET devices.  Annealing at high temperatures (>900~C),
drives impurities (e.g., boron or phosphorus) from the glass into the
silicon substrate adjacent to the gate electrode.  This highly doped
channel provides performance enhancements by reduction of
source/drain resistance.  The use of N-doped and P-doped glasses can
be used to make complementary FET technologies (CMOS).  The reduced
resistance of these shallow extensions under the gate sidewalls
becomes more pronounced as the devices are cooled to liquid nitrogen
temperatures for high performance applications.  The use of very
shallow extensions allows true scaling to sub-half micron dimensions.

      The structure thus described is shown in Fig. 1. Conventional
polysilicon gates 1 are formed over a gate oxide 2 by standard
processing techniques.  A doped glass, such as borosilicate glass or
phosphosilicate glass, is deposited on the wafer surface.  An
anisotropic RIE is per...