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Synchronous Loop Halter Disclosure Number: IPCOM000121376D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 45K

Publishing Venue


Related People

Clark, LJ: AUTHOR [+1]


This invention is applicable to computers containing multiple processors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 87% of the total text.

Synchronous Loop Halter

      This invention is applicable to computers containing
multiple processors.

      Computers containing multiple processors, such as the 3090*,
are prone to synchronous loops between the storage control element
and the processors.  These loops will deadlock the system if left
unchecked.  These loops are caused by multiple requesters getting
priority at fixed timing intervals such that other requesters never
get serviced.  To fix these loops it is necessary to introduce a
random request in the storage control element, thus changing the
timing interval and breaking the loop.

      The invention to accomplish this consists of adding a new
requester to the priority in the storage control element.  This new
requester consists of a pseudo random generator, which defines the
interval between requests and the duration of the request, a hold
latch and a new line into the priority controls, as shown in the
figure.  This new requester has the highest priority in the storage
control element.  Thus, it will override any request from another

      The pseudo random generator consists of a polynomial counter
and two AND gates.  The AND gates decode a subset of the bits in the
polynomial counter.  The selection of bits is arbitrary and may be
programmable to give different random patterns.  By decoding a subset
of bits in the counter, it is possible to create pseudo random
requests in the storage control element.