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Improved Isolation on a Distributed Bus Disclosure Number: IPCOM000121417D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 53K

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Lucas, GS: AUTHOR [+2]


This invention allows a distributed bus design to have better isolation and detection.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Improved Isolation on a Distributed Bus

      This invention allows a distributed bus design to have better
isolation and detection.

      The distributed bus is an eight-bit bus with no parity (parity
is generated internally in the microprocessor).  The distributed bus
does not have any parity because there are two cards in the system
and each card generates four bits. Since neither card knows what the
other is sending parity is not contained in the bus.  Each bit on the
distributed bus is used to communicate with a channel, so when the
microprocessor uses the distributed bus it communicates with four
channels on one card and four other channels on the other card.  The
microprocessor also has a common bus which it uses when needing to
communicate with eight channels of one card.  This bus does have
parity associated with it.

      The previous design of the distributed bus had no hardware
isolation and detection of the bus breaking, because the design only
used the distributed bus.  The module in the card received the bits
without parity and sent back the bits without parity.

      The new design will latch the eight bits of data and the parity
bit during a write using the common bus and check for good parity,
even though only four bits will be used by that specific card.  When
the microprocessor reads the distributed register only four bits of
data are sent. Parity is checked on the eight bits and parity bit of
the register on the card before the...