Method to Utilize High Level Logic Design Language for CMOS2 Designs Using Release Interface Transmittal A/B
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
This article describes a method which provides a means of changing only the gate array portion of a chip while holding the standard cell portion constant.
Method to Utilize High Level Logic Design Language for
Using Release Interface Transmittal A/B
describes a method which provides a means of
changing only the gate array portion of a chip while holding the
standard cell portion constant.
synthesis system (LSS) program is used to generate
chip basic design language for structure (BDL/S) for fabrication.
When the release interface transmittal (RIT) A/B option of the CMOS2
technology is desired, certain requirements must be met. These
requirements involve freezing the standard cell portion of the chip
between RIT A and RIT B.
generates BDL/S without regard to standard
cell/gate array content, so it is impossible for LSS to meet the
requirements set forth. LSS may, for example, place a certain block
on a different sheet, or give a net a different netname, from one run
to the next, even if there were no changes to that particular block
or net. The method disclosed herein provides a means of using LSS
while meeting the requirements for RIT A/RIT B processing.
on users of the RIT A/RIT B capability of the
CMOS2 technology are as follows:
1. The RIT A must contain all the standard cell and gate array
books of the chip.
2. The RIT B must contain all the standard cell and gate array
books of the chip.
3. Any standard cell book present in the RIT A must appear in the
RIT B with exactly the same block-serials, netnames and placement
the standard cell portion of the chip cannot be
changed in the RIT B step.
The BDL/S can
be conceptually divided into two pieces, the
standard cell portion and the gate array portion. Once these
portions are identified, the nets which cross from one portion to the
other can be identified. This procedure involves:
1. Identifying the netnames (names for each connection of
the logic blocks within a chip) which cross from one
portion to another, and forcing those nets to a certain
unique value. This is done in such a way that it is
reproducible, using a logic transformation system
2. Saving the standard cell books from this RIT A level.
3. Generating a new level of BDL/S for RIT B without
changing the portion of the logic for the standard
4. Removing the new standard cell books and replacing them
with the old standard cell books that were saved in
step 2 above.
is now described in more detail. Refer