24 MHz Grey Coded State Machine for Adapting 12 MHz Synchronous Bus Interface Logic to AS/400 I/O Bus
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Farrell, JK: AUTHOR [+3]
A technique is described which is a solution to a generic and inherent problem which results when bus interface logic designed for a fast technology is adapted to a slower technology.
24 MHz Grey Coded State Machine for Adapting 12 MHz
Interface Logic to AS/400 I/O Bus
is described which is a solution to a generic
and inherent problem which results when bus interface logic designed
for a fast technology is adapted to a slower technology.
the 24 MHz grey-coded state machine described
herein is implemented in the integrated service digital network
(ISDN) module (IIM) which is in a 1.5 micron technology intended for
low- cost, high-volume ISDN basic rate products. The IIM design has
6 time division multiplexed (TDM) channels running at a clock
frequency of 12 MHz. The IIM is designed in a relatively slow
technology compared to the integrated data link controller (IDLC)
which has 32 TDM channels running at a clock frequency of 20 MHz. The
IDLC is in a 1.0 micron technology intended for high-cost, low-volume
Primary Rate ISDN products. Both modules interface to the same
AS/400* I/O bus and use the same TDM logic. The IIM uses a slower
speed technology (and slow clock) for the TDM logic than the IDLC.
The slower clock (80ns) presented a problem for interfacing to the
AS/400 I/O bus which has signals which may only be present for 60 ns.
These sampled signals could be lost by the IIM. In order to preserve
both the bus interface logic and and TDM logic originally designed
for the IDLC, without change, it was determined the IIM could be run
at 12 MHz, but a small amount of logic which directly generated
signals on the AS/400 I/O buses would have to be added and run at 24
MHz (twice the frequency of the TDM logic and common bus interface
logic). The use of a 2-bit state machine which is 'grey-coded'
imposes no requirement for clock phase relationships to exist between
the 12 and 24 MHz clocks and is seen as a generic solution to this
illustrates the use of the 2-bit 24 MHz state
machine used for the DTACK_ signal generated by the IIM. The DTACK_
signal is the Data Acknowledge signal used by the Motorola 68000
Microprocessor on the AS/400 I/O bus. DTACK_ is active low and is
used to indicate to the 68000 microprocessor that data has been
latched by a slave device on a write cycle or is available on a read
cycle. The 12 MHz logic from the IIM uses type D latches with no
reset capability, a standard 'data gating' techniq...