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# Floating Point Post Normalization Without LZA/LZD Circuits

IP.com Disclosure Number: IPCOM000121789D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 59K

IBM

## Related People

Chu, TV: AUTHOR [+2]

## Abstract

The post-normalization on floating point results is required according to IEEE standard, to postnormalize datum and count leading zeros. This counting requires a lot of circuits. These circuits are too large to be used in this processor, but can be used in the high-end machines. These circuits are called LZA (leading zero anticipator) and LZD (leading zero detector).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Floating Point Post Normalization Without LZA/LZD Circuits

The post-normalization on floating point results is
required according to IEEE standard, to postnormalize datum and count
leading zeros.  This counting requires a lot of circuits. These
circuits are too large to be used in this processor, but can be used
in the high-end machines.  These circuits are called LZA (leading
zero anticipator) and LZD (leading zero detector).

The floating point design is made to execute mainly a large
math primitive called MADD (multiply add).  The two operands, A and
C, are multiplied and then added to B operand.  To do the addition
part, an alignment is required between the result of A*C and the
operand B.  There is a technique used to optimize the alignment,
which is to position the B operand 56 bits ahead of the result of
multiplication and adjust their exponent amounts.  The alignment will
then be only one- directional (right shift). This technique is useful
to simplify the shifters and make them faster.

In our floating point, this technique was used to eliminate the
LZA and LZD circuits.

As B shifts to the right, we fill with leading zeros. When the
shift count (Sc) is less than 56, we know the number of leading zeros
in the result.

(Image Omitted)

For a logical addition of two numbers, a carry out of the msb
may reduce the number of leading zeros by 1.  For a logical
s...