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Aggressively Scaled Submicron-Emitter Vertical Heterojunction Bipolar Transistor

IP.com Disclosure Number: IPCOM000122214D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 155K

Publishing Venue

IBM

Related People

Kirchner, PD: AUTHOR [+3]

Abstract

Described is a heterojunction bipolar transistor that is designed for very high speed while maintaining large current gains. The transistor is designed to overcome problems inherent with conventional designs which have both a larger emitter-base capacitance and a large base access resistance which cause the transistors to switch slowly.

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Aggressively Scaled Submicron-Emitter Vertical Heterojunction Bipolar
Transistor

      Described is a heterojunction bipolar transistor that is
designed for very high speed while maintaining large current gains.
The transistor is designed to overcome problems inherent with
conventional designs which have both a larger emitter-base
capacitance and a large base access resistance which cause the
transistors to switch slowly.

      Typically, state-of-the-art bipolar and heterojunction bipolar
transistors (BJT and HBT) processes require many steps, including
numerous mask levels with submicron dimensions for both features and
alignment tolerances. Prior art [1] indicates that by shrinking the
active emitter width in a Si BJT to 0.35 m, a switching time of 30
ps can be obtained.  In another prior art demonstration [2], an
AlGaAs HBT can achieve a switching time of 27 ps with a 1.5 m emitter
and is expected that a comparable reduction of the emitter width in
an AlGaAs HBT will result in markedly better switching times than the
corresponding Si devices.

      Unfortunately, the process complexity of bipolar technologies
is reflected in low device yields which, in turn, limit the circuit
complexity to that which results in a minimum acceptable yield of
functioning chips.  It is clear that any technique which decreases
the number of processing steps is likely to decrease the cost per
chip and either increases the yield of working chips or increases the
number of circuits that can be accommodated on a chip at a given
yield.

      The concept described herein is designed to produce an AlGaAs
HBT with emitter widths of approximately 0.5 m with only one 1-2 mm
lithography step and having no critical alignment problems.  The
process involves an N-p-n transistor, but by switching the "n" and
"p" designations, a P-n-p transistor can be produced.  The design
starts with a planar MBE-grown structure, as shown in Fig. 1, that
contains: an n-GaAs emitter layer topped with N-AlGaAs; an undoped
GaAs layer; a p-GaAs base contact layer; an undoped GaAs buffer and a
thin AlGaAs capping layer.  The structure is removed from the MBE and
standard optical lithography and etching are used to define
approximately 1 mm-wide holes in the AlGaAs capping layer.  Then the
wafer is placed back in the MBE system for the sublime step, where it
is heated to approximately 700~C in an As2 flux for approximately one
hour, where the AlGaAs cap has been removed and V-shaped grooves are
created, as shown in Fig. 2.  In this case, the grooves will be
flat-bottomed because the etching will stop on the AlGaAs emitter
structure.

      In-situ regrowth is used next.  The following layers are grown
in sequence:  The active base region (p-GaAs) is grown at a low
temperature to obtain conformal regrowth; then an n-GaAs collector is
grown at a high temperature to obtain a flat "refill"-mode regrowth;
then a nlayer with contact metallurgy is grown.  The wafer is...