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Multiple Thickness Silicon On Insulator Films

IP.com Disclosure Number: IPCOM000122219D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 43K

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Related People

Davari, B: AUTHOR [+4]


This article describes a planar structure with multiple thicknesses of silicon on insulator (SOI).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Multiple Thickness Silicon On Insulator Films

      This article describes a planar structure with multiple
thicknesses of silicon on insulator (SOI).

      When SOI is used as the material for fabrication of CMOS and
lateral bipolar structures, it is desired that the thickness of SOI
for CMOS be reduced as much as possible (to improve on device
characteristics) and the thickness of the film for the bipolar part
be increased as much as possible (to increase the emitter width and
current derive).  This raises the need for multiple SOI film
thicknesses.  The basic structure is presented in the figure. It
contains a planar structure, containing multiple SOI film thickness.
This structure can be fabricated using epitaxial lateral overgrowth
and chemical mechanical polishing, similar to the method described in
[*].  The fabrication sequence is as follows: on silicon wafer oxide
is grown and polish stop is deposited.  Next large SOI areas are
opened in polish stop. Then using additional masks, the oxide
thickness is reduced in the areas that thick SOI film is needed.
This step has to be repeated as many times as needed, depending on
the number of thicknesses desired. Next seed areas are opened and
selective silicon epitaxy is done. After polishing and removal of
polish stop and oxidation of seed area (as described in [*]) multiple
thickness SOI film is obtained (see the figure).

(*)  G. Shahidi, B. Davari, Y. Taur, J. Warnock, M. R. Wordeman, P....