Browse Prior Art Database

Micro Channel Emulation Tester for Busmaster Adapter Cards

IP.com Disclosure Number: IPCOM000122247D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Kelleher, RJ: AUTHOR [+3]

Abstract

A test system is designed to evaluate a PS/2* Micro Channel* BusMaster card for its response to variations of critical bus timings in the following modes: 1. I/O slave 2. Arbitration 3. DMA or I/O busmaster The test system is composed of: 1. A commercially available ASIC verification system with a 50 MHz minimum vector rate (such as the Tektronix LV500 or the HP 82000) 2. A 200 MHz logic analyzer (such as the Tektronix DAS 9200) 3. A test card designed to function as a memory of I/O slave. The timings this card produces as feedback are programmable. 4. A "load" BusMaster card to be used as a contender during arbitration cycles. This can be any existing BusMaster card. 5. The BusMaster Card Under Test (CUT) 6. A fixture and cabling used to bus all the above components together.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Micro Channel Emulation Tester for Busmaster Adapter Cards

      A test system is designed to evaluate a PS/2* Micro
Channel* BusMaster card for its response to variations of critical
bus timings in the following modes:
1.  I/O slave
2.  Arbitration
3.  DMA or I/O busmaster
The test system is composed of:
1.   A commercially available ASIC verification system with a 50 MHz
minimum vector rate (such as the Tektronix LV500 or the HP 82000)
2.   A 200 MHz logic analyzer (such as the Tektronix DAS 9200)
3.   A test card designed to function as a memory of I/O slave.  The
timings this card produces as feedback are programmable.
4.   A "load" BusMaster card to be used as a contender during
arbitration cycles.  This can be any existing BusMaster card.
5.   The BusMaster Card Under Test (CUT)
6.   A fixture and cabling used to bus all the above components
together.
The figure shows a block diagram of the test system.

      The ASIC verification system 1 is used to emulate the timings
and provide the signals normally provided by a PS/2 system board.  It
initializes the CUT 5 and the "load" BusMaster card 4 and programs
the desired timings into the I/O Memory slave 3.

      The ASIC verification system 1 is then used to delay or advance
the timings of interest in steps while running an evaluation program,
providing a "go/no go" response to each step of timing variation
based on the performance of the CUT 5.

      The tester configuration of the fi...