Browse Prior Art Database

Enhancing Board Functional Self-Test by Concurrent Sampling

IP.com Disclosure Number: IPCOM000122293D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 131K

Publishing Venue

IBM

Related People

Wagner, KD: AUTHOR [+1]

Abstract

Disclosed is a general method to enhance board test and diagnosis, potentially adding every chip I/O pin as an observation point observed frequently and coupled to functional self-test. It requires concurrent sampling of signals at chip boundaries, compressing this data, and verifying its signature in-line in the code. Tests continue to execute at the normal board operating speed. Method

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Enhancing Board Functional Self-Test by Concurrent Sampling

      Disclosed is a general method to enhance board test and
diagnosis, potentially adding every chip I/O pin as an observation
point observed frequently and coupled to functional self-test.  It
requires concurrent sampling of signals at chip boundaries,
compressing this data, and verifying its signature in-line in the
code.  Tests continue to execute at the normal board operating speed.
Method

      Functional self-test (FST) consists of an on-board (or
off-board) processor executing test code to verify correct operation
of the board- under-test (1,2).  The processor applies the stimulus,
observes the response, compares with the expected value(s), and acts
on any errors.  Test code blocks resemble:
      (known board state)
...
DO < Operation n >
COMPARE < Response with Predicted Value >
BRANCH ON CONDITION < Not Equal >
      TO ERROR HANDLER(n)
...

      To enhance the process, while the FST code executes
continuously (controlled by the board oscillator) at predetermined
intervals, the boundary scan elements strobe data at the chip I/Os
using the sample clock(s).  This sampled data is downloaded via scan
into a compressor using the scan clock(s) while the processor
continues to execute code.  This unit of operation is called the
sample-scan cycle.

      A sample-scan cycle test consists of initialization, multiple
sample-scan cycles, and signature verification.  If the compressor is
an addressable I/O register, the processor may read and verify its
contents (the signature) in the FST code; otherwise, it may be
checked by the test controller. Two options are shown for the two
concurrent processes during execution of the FST code segment.  If
the sample-scan cycle repeats at regular intervals, it is called
free-running.  As an alternative, the processor itself (through the
FST code) may control the sample-scan cycles. In this case, it must
be able to set a register bit which is reset by sample-scan control
circuits.
                         FREE-RUNNING
                Process 1                Process 2
               (Processor)             (Sample-Scan)
RESET                                   INITIALIZE
...
EXecute CodeBlk1                        Sample
Execute CodeBlk2                        N Scan Clocks
EXecute CodeBlk3                        Sample
...                                    N Scan Clocks
EXecute CodeBlkn                        ...
...                                    STOP
READ Compressor
COMPARE
BRANCH < Not Equal >
   to ERROR_HANDLER
END
...
                     PROCESSOR-CONTROLLED
                Process 1   ...