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Priority Management on a Shared Data Bus

IP.com Disclosure Number: IPCOM000122371D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 50K

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Cukier, M: AUTHOR


Disclosed is a hardware circuit intended to improve the efficiency of a shared data bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Priority Management on a Shared Data Bus

      Disclosed is a hardware circuit intended to improve the
efficiency of a shared data bus.

      Figure 1 shows a bus shared between different circuits, such as
circuit 1, circuit 2, circuit 3, etc.

      At the same time, all the 3 circuits might want to access the
bus. In order to solve the contention problem which results
therefrom, an access manager is provided.

      Since several circuits might want to send or receive data on
the shared bus, a priority rule is required.

      When a circuit wants to access the bus, it activates a
so-called access request (ar) signal. The access manager decides
which among the circuits should use the bus, and activates one and
only one access granted (ok) signal.

      This proposal describes a dynamic priority rule. This dynamic
priority rule allows:
      1.   in normal mode of operation to give priority to circuit 1
      2.   if a failure occurs that causes circuit 1 to monopolize
the bus, the suggested solution gives high priority to circuit 2.

      This dynamic priority rule (Figure 2) works as follows:
      1.   In normal mode of operation, the circuit 1 has a priority
higher than circuit 2.
      2.   When circuit 2 requests a bus access, it starts a counter.
      3.   If the circuit 2 obtains the ok from the access manager,
there is no need to modify the priority, and the counter is reset.
      4.   When...