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High Speed, Collector Up Silicon Heterojunction Bipolar Transistor Structure

IP.com Disclosure Number: IPCOM000122447D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 144K

Publishing Venue

IBM

Related People

Chu, J: AUTHOR [+3]

Abstract

Disclosed is a process for fabricating a collector-up silicon heterojunction bipolar transistor structure in a form suitable for integration.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed, Collector Up Silicon Heterojunction Bipolar Transistor
Structure

      Disclosed is a process for fabricating a collector-up
silicon heterojunction bipolar transistor structure in a form
suitable for integration.

      At present, one of the main limitations on reducing propagation
delay of ECL circuits is the parasitic elements associated with the
transistor structure.  It has been shown in gallium arsenide-based
technologies that the collector-up structure has much-reduced
parasitics [*].  Our estimates show that as much as 40% improvement
in performance may be expected from using a collector-up structure
for a graded-base transistor with fr in the vicinity of 100 GHz.

      The proposed structure (Fig. I) is completely self-aligned, and
uses all low-temperature (< 650oC) processing after formation of the
strained base layer, to reduce stress on the structure.  In addition,
alignment of collector-base and emitter-base areas is made by use of
a sidewall, without the requirement of an additional lithography
step.

      The process starts with a p- wafer.  The first step is
formation of a "sub-emitter" by arsenic implant and drive-in.  Next,
the deep trench isolation is formed (Fig. A).

      Next, the emitter-base-collector stack is grown.  This consists
of a 50 nm, 3E18 n-layer, a p+ 30-60 nm silicon-germanium base, and a
200 nm 4E17 n-doped collector layer.

      Next, an N+ collector contact layer, consisting of in-situ
phosphorus-doped amorphous silicon is deposited by LPCVD.  This layer
is recrystallized at 650oC to form a low-resistance contact layer for
the collector.  Finally, a dielectric stack consisting of 4 nm HIPOX,
25 nm deposited nitride, 25 nm poly and 150 nm deposited nitride is
formed. The topmost nitride layer is used as a polish-stop lever
(Fig.  B).

      A lithographic step is used to define the collector area.
There is no other lithography step that requires critical alignment.
The dielectric stack is then etched using RIE, and the silicon is
etched using a timed etch, to stop before the base layer is reached.
A sidewall is formed using 25 nm HIPOX and 25 nm deposited nitride
(Fig. C). Another RIE etch of silicon-germanium selective to nitride
is used to etch throug...