Browse Prior Art Database

Nonlinear Bit Shift Compensator

IP.com Disclosure Number: IPCOM000122519D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Braden, JJ: AUTHOR [+5]

Abstract

An algorithm for preshifting (precompensating) data bits before being written to a magnetic medium is disclosed. The algorithm contains an analog and logic section to provide the necessary clock signals and a data precoding function of 1/(1-D**2).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

Nonlinear Bit Shift Compensator

      An algorithm for preshifting (precompensating) data bits
before being written to a magnetic medium is disclosed.  The
algorithm contains an analog and logic section to provide the
necessary clock signals and a data precoding function of 1/(1-D**2).

      The algorithm incorporates part of the data precoding (in
finite field arithmetic) along with the precompensation analog
circuitry.  The analog section of this algorithm incorporates the use
of delay books along with a DAC (digital to analog converter) so that
a variable amount of precompensation can be achieved.  Also the
analog circuitry uses a divide by two flip-flop to provide part of
the data precoding.

      A simplified block diagram of this precompensation scheme is
shown in Fig. 1.  The logic circuitry combines the CLK and DATA
signals in a 1/(1+D) function and drives the analog circuitry with
(DATA/CLK) information.  The DATA/CLK signal is processed by two
analog delay books.  One delay book has a fixed delay of C units,
while the other delay book has a variable delay of C+D units.  The
variable delay book is controlled by a current DAC that is driven by
the logic section.  The logic section also sends out a PRECOMP THIS
BIT signal which is based on the data pattern being processed by the
1/(1+D) logic function.

      In normal operation (No Precomp), the multiplexer selects the A
signal to clock the rising edge-triggered flip-flop.  The flip-flop
i...