FPU Overflow/ Underflow Detection

FPU Overflow/ Underflow Detection

      The IEEE Standard for binary floating point requires
normalization and rounding on the results of arithmetic operations.
Only after normalization and rounding can overflow or underflow be
detected.  In this floating point, this process of normalization and
rounding is done at the writeback cycle.  If the overflow/underflow
detection is not calculated until after normalization and rounding,
the overflow/underflow hold signal would be intolerable late in the
cycle.  Our goal was to find an adequate guess mechanism which would
be relatively simple to implement and would eliminate this long hold
path.

      The figure details this floating-point writeback cycle. Two
restrictions are important to keep in mind.  First, we can normalize
at most 16 positions in a single cycle.  If additional normalization
is required, the feedback path enables us to loop on the writeback
cycle.  Given this restriction, normalization can subtract at most 16
from the intermediate exponent.  The second restriction is that
rounding can add at most 1 to the intermediate exponent. With these
restrictions in mind, it is obvious that a prediction based on the
intermediate exponent is extremely close to the actual
overflow/underflow detection.
     The Maximum exponent value Emax = +2046 (in excess 1023 format).
     The Minimum exponent value Emin = +1 (in excess 1023 format).
     Let Ei = the intermediate exponent of arithmetic operation...