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Serial I/O Channel to T3 Switch Disclosure Number: IPCOM000122587D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 119K

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This article describes the use of packets of data over multiple links to achieve a higher data rate than a single link is capable of doing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Serial I/O Channel to T3 Switch

      This article describes the use of packets of data over
multiple links to achieve a higher data rate than a single link is
capable of doing.

      When attempting to design a high-speed channel attachment from
computer to computer, two limitations are immediately encountered,
speed and distance.  These have always been traded-off, depending on
the application requirements (e.g., very fast meant co-located, local
channels while very far meant using communications facilities with
inherent bottlenecks and design problems).

      The recent end-user availability of the communications facility
called "T3" has partially resolved this by creating 45 Mb/s
connections coast-to-coast.  While a significant improvement over
"T1" (1.5 Mb/s facilities), T3 still requires parallel connections to
support the proposed 200 Mb/s optical serial I/O channel (SIOC) for
future mainframes.  In the communications carrier environment,
parallel paths create a serious problem in synchronization,
particularly when several carriers are involved as in a cross-country
route, or for back-up diversity.

      The common approach is to utilize fiber-optic transmission
facilities to eliminate the parallel path requirement.  The drawback
to this approach is that it creates a non-redundant route.  T3
switched facilities are common, and multiple levels of redundancy are
inherent in the network.

      An architecture is described herein that utilizes T3
facilities, is T3 digital access cross-connect compatible, is
implementable with a relatively low-speed circuit switch, and removes
the major source of synchronization and radiation problems.  The
description assumes the current 200 Mb/s design point of the SIOC,
but it could be applied to higher speed inputs by appropriate
expansion in the number of T3 outputs.

      Referring to the drawing which is a functional block diagram of
the disclosed design, the architecture has an input adapter 1 that is
basically a serializer/deserializer (SERDES) function with multiple
buffers 4, a digital space circuit switch 2 of MxN construction, a
set of output adapters 3 that convert a high-speed bit stream into a
packet with T3 format, and fiber-optic buses 5.  Not shown in the
figure is the controller function for these elements (the device that
sets up the routes from computer to computer, handles the error
recovery, etc.) since this function could be an imbedded set of
processing or an application on one of the attached computers.

      The operation consists of using multiple 45 Mb/s T3 circuits to
transport a single 200 Mb/s SIOC channel.  The SIOC transfers blocks
of data, then waits for a response. Therefore a mismatch of input to
output speeds (200 to 180 Mb/s) is acceptable.  If allowanc...