Browse Prior Art Database

MIMD Parallel Architecture with Critical Path Acceleration

IP.com Disclosure Number: IPCOM000122602D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 97K

Publishing Venue

IBM

Related People

Childs, PL: AUTHOR [+4]

Abstract

Disclosed is an architecture for a parallel processor which speeds execution at the nodes by using a "Critical Path Hardware" (CPH) consisting of programmable hardware. The CPH is used to speed the critical path section of application code and, because the logic is placed in hardware, critical path acceleration is increased.

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MIMD Parallel Architecture with Critical Path Acceleration

      Disclosed is an architecture for a parallel processor
which speeds execution at the nodes by using a "Critical Path
Hardware" (CPH) consisting of programmable hardware.  The CPH is used
to speed the critical path section of application code and, because
the logic is placed in hardware, critical path acceleration is
increased.

      MIMD parallel machines provide significant speed-up for a large
class of parallel programs.  The general construction of an MIMD
parallel processor is modified as shown in the figure to provide
additional speed-up.  Here, there are many node processors connected
through some type of communication network.  Each of the nodes
contains its own copy of the program and data, residing in the local
memory at the node.  Therefore, each node is a classical von Neumann
machine.  Because of this, each program at the node will suffer from
serial operation of the critical path through the code.  With the
CPH, acceleration of the critical path is achieved using programmable
hardware.  This solution avoids the pitfalls of special-purpose
hardware by implementing the critical path accelerator in
programmable gate arrays.  Therefore, a large class of algorithms can
perform critical path operations more quickly on the identical
implementation of the machine.  The programmability of the software
solution is preserved and a speed advantage is gained by executing
the critical path in hardware.

      Each node interconnects to neighbors in the processor array.
Because this concept is directed at increasing the execution speed of
individual node processors, it is topology independent.  Therefore,
any node interconne...