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Early Sticky Calculation for This Floating Point

IP.com Disclosure Number: IPCOM000122612D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Chu, TV: AUTHOR [+2]

Abstract

The IEEE execution model for double precision: L FRACTION G R X bit---> 0 1....52 53 54 55

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Early Sticky Calculation for This Floating Point

      The IEEE execution model for double precision:
           L FRACTION  G   R   X
bit--->   0  1....52  53  54  55

      The sticky bit, 'X', is defined as the OR of all bits below the
Round bit, 'R'.  However, the mantissa is not in the above format
until after normalization.  Waiting to calculate the entire sticky
until after normalization causes two problems.  First, there would be
a huge number of bits dragged through the dataflow just for sticky
calculation. With the severe space restrictions of this floating
point, reducing the number of unnecessary bits through the dataflow
is very important.  The second problem with waiting to calculate the
sticky would be the performance impact.  The output of the normalizer
feeds directly into the rounder.  Since the final sticky bit is
required to round properly, calculating the sticky bit off the
normalizer output would slow down our round control.

      This floating point has broken up the sticky calculation into 5
sections spanning 3 pipeline stages.  Our primary goal was to find a
balance between reducing the excess dataflow baggage and the hardware
costs of determining that intermediate sticky.  A secondary
consideration was to minimize the number of bits remaining to be ORed
by the time normalization was complete.  This would reduce the delay
in the round control.
      1.   Output of the alignment shifter (multiply cycle).

      The B operand will align to the 'A*C' by right shifting B until
the exponents are equal.  Notice that the smaller B is relative to
'A*C'; the more of B will be shifted totally below 'A*C'.  Given the
IEEE execution model above, any portion of B shifted below the dashed
line can be ORed into sticky.
      2.   Output of the main adder/incrementer (add cycle)

      If the normalization determines a shift by 0, then the first
'1' is within the top 16 bits.  Therefore, we can OR the 48 LSB's
into sticky.

      If the normalization determines a shift of 16, then the first
'1' is between position 16 and 32.  Therefore, we can OR the 32 LSB's
into sticky.

      If the normalization determines a shift of 32, then the first
'1' is between position 32 and 48.  Therefore, we can OR the 16 LSB's
into sticky.

      If the normalization determines a shift of 48, then the first
'1' is below position 48 but is not exactly known. Therefore, we
cannot OR any bits into sticky.

      The writeback cycle is capable of normalizing the mantissa up
to 16 bits in a single cycle.  If additional normalization is
required, we feed the mantissa back to the normalization latch and
will l...