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Novel Chip Image for Reduced Wiring Lengths

IP.com Disclosure Number: IPCOM000122664D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Koehl, J: AUTHOR [+2]

Abstract

This article describes the rotation of the chip image by 45~ and the reduced wiring lengths thus obtained as determined by mathematical means.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

Novel Chip Image for Reduced Wiring Lengths

      This article describes the rotation of the chip image by
45~ and the reduced wiring lengths thus obtained as determined by
mathematical means.

      Advanced technologies on multichip modules (MCMs) and silicon
carriers are used to implement highly interconnected logic
structures.  Pins are connected to a number of devices which, in some
cases, are arranged remote from each other. Frequently, a plurality
of signals are required for connecting circuits on opposite chip
corners.

      In state-of-the-art technologies (chip, ceramic MCM and silicon
carrier), the wiring tracks are parallel to the chip edges.  A
typical chip image currently used is marked as B2. With the novel
concept, the chip image is rotated by 45~ (B1), retaining the
preferred horizontal and vertical wiring directions.  This reduces
the maximum distance between 2 cells on a chip by 41%.  The average
wiring length from a given cell to any other cell on the chip is
reduced as well, as is the maximum signal propagation time between
any two chip circuits for two- point connection, which is minimized.
As the longest (critical) path determines the chip cycle time, this
evidently leads to improved system performance, whereas the reduced
average distance between any two cells improves the wirability.

      It could be shown by mathematical means that the proposed chip
image reduces the average distance between one and any other point on
the chi...