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Column Redundancy for Fast Memory Arrays

IP.com Disclosure Number: IPCOM000122673D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 99K

Publishing Venue

IBM

Related People

Wong, R: AUTHOR

Abstract

When memory array redundancy was introduced, it was applied to arrays of fixed data width. The 9/10 bit redundancy scheme had been used in many older products, where the data path was nine bits wide, and a tenth spare bit column was provided for repair purpose. When the high- end arrays became more complex with variable configurations, the data path was no longer of fixed width, and the 8/9 word redundancy was then applied. This horizontal repair technique was further extended to electronic relocate, where any five single word lines can be repaired from five spare word lines.

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Column Redundancy for Fast Memory Arrays

      When memory array redundancy was introduced, it was
applied to arrays of fixed data width.  The 9/10 bit redundancy
scheme had been used in many older products, where the data path was
nine bits wide, and a tenth spare bit column was provided for repair
purpose.  When the high- end arrays became more complex with variable
configurations, the data path was no longer of fixed width, and the
8/9 word redundancy was then applied.  This horizontal repair
technique was further extended to electronic relocate, where any five
single word lines can be repaired from five spare word lines.

      In the HARPNP arrays, memory cells tend to interact more
strongly with the bit lines than the word lines.  A bad cell tends to
ruin the whole bit column more than it affects the whole word line.
Also the bit column control circuits for sense, write and select are
very complex and have to be packed into a very narrow pitch,
contributing to a higher frequency of bit line failures.  All these
are consistent with the fact that in the HARPNP products, bit fails
are prevailing over word fails.

      Besides, the column redundancy is less costly in power and
performance:
(1)  The unselected word line driver dissipates more power than the
selected word line driver, while the unselected bit line driver
dissipates no power.  Thus, spare bit column circuits are power-
free.
(2)  More word lines will add to the cell back injections. Cell back
injections are the wasted power that also slow down the HARPNP array
access.

      Therefore, column redundancy is much more preferable to the
conventional word redundancy scheme that has been used in the
high-end arrays for many years.

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