V-Shaped Thin Plate Lateral PNP Transistor With a Self Aligned Polysilicon Collector Contact

V-Shaped Thin Plate Lateral PNP Transistor With a Self Aligned Polysilicon
Collector Contact

      Described is a dense and thin-base lateral PNP transistor
that is compatible with vertical NPN transistor fabrication. The
device provides high performance and high density complementary
bipolar circuitry.  Also, the process flow is described for the
fabrication integration of the V-shaped lateral PNP and the high
performance vertical NPN complementary bipolar device.

      Typically, complementary bipolar integrated circuits are used
in digital logic applications where PNP transistors are not just a
load device but are an active switching device, similar to NPN
transistors.  The concept described herein produces a high
performance V-shaped lateral PNP transistor which contains a thin
base and has a low parasitic emitter-base junction and minimum
minority carriers, storage, etc.  The V-shaped lateral PNP has a
similar device layout to a vertical NPN like structure and provides
low parasitic capacitance and higher density for integrated circuit
requirements.

      Fig. 1a shows a cross-section of the V-shaped PNP device.  For
reference comparisons, Fig. 1b shows a cross-section of an existing
state-of-the-art vertical NPN transistor.  It can be seen that the
similarities are comparable.  Figs. 2a to 2e show the process flow
for the fabrication of the V-shaped lateral PNP transistor.  The
process is as follows:
     a) The process flow follows the standard transistor fabrication
process for NPN transistors up to p     polysilicon stack etching, as
shown in Fig. 2a.
     b) Boron implantation is then performed to form a p- well in the
p+ poly open area.  The boron drive-in from the p poly layer is then
performed followed by thermal oxidation of the silicon surface and
deposition of the nitride/polysilicon film for the sidewall.  The
device cross-section at this stage of fabrication is shown in Fig.
2b.
     c) The sidewall is then formed by RIE etching.  The first
etching of polysilicon ends on the nitride.  Then phosphorous
implanta       tion is performed to form a n+ guard-ring underneath
the side       wall oxide.  The device cross-section at this stage of
fabrica       tion is shown in Fig. 2c.  As an option, another higher
energy phosphorous implantation can also be added to provide a
pedestal n+ region.  This option is shown in Fig. 2c.  The pedestal
is used to ensure that the PNP base region provides a good electrical
link to the higher n+ sublayer, as shown in Fig. 1a.
      d) The sidewall etching is then completed through nitride/oxide
etching end-pointing on silicon.  Using nitride/oxide as a mask, a
silicon V-groove etch, using KOH solution, is made. This anisotropic
etch is self-limiting in depth since the V-surfaces [(III)planes]
etch very slowly.  The p-well depth is designed to be approximately
the same as the V-groove depth.  The polysilicon on the sidewalls i...