Browse Prior Art Database

Method and Apparatus for Reducing Instruction Cache Trailing Edge Effect

IP.com Disclosure Number: IPCOM000122782D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Flynn, WT: AUTHOR [+2]

Abstract

Disclosed is a method for reducing the trailing edge effect of instruction cache (I-Cache) line fills. The last subline write is delayed in order to access a branch target, thus reducing latency.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method and Apparatus for Reducing Instruction Cache Trailing Edge
Effect

      Disclosed is a method for reducing the trailing edge effect of
instruction cache (I-Cache) line fills.  The last subline write is
delayed in order to access a branch target, thus reducing latency.

      A line fill for an instruction cache can take multiple
cycles.  For instance, if a cache structure has four sublines and the
width of the bus to write the cache is one subline long, four cycles
are required to write the instruction cache.  If the given design
bypasses the instructions into the instruction queue/buffers for
dispatch, then  the processor can start execution of the instructions
while the line fill is taking place.  If one of the bypassed
instructions is a branch,  then an instruction cache read access is
required to fetch the branch target instructions.  An instruction
cache that is single-ported would  not be accessible while the line
fill is taking place.  The branch instruction would be stalled
waiting to access the instruction cache while the rest of the line
fill took place, potentially stalling instructions behind it.  A
two-ported array, in which a read and write  could occur at the same
time, would double the size of the array. This  would be a costly
solution as area is almost always a premium.

      If there is a branch waiting to access the instruction cache,
the last subline is written one cycle later.  The branch accesses the
instruction cache during the f...