Browse Prior Art Database

Silicon Wafer Contouring - High Precision Ring Shape

IP.com Disclosure Number: IPCOM000122994D
Original Publication Date: 1998-Mar-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Cazcarra, V: AUTHOR [+1]

Abstract

With the rapid introduction of 300mm silicon wafers and the development of larger VLSI chips, the edge shape of wafers appears to be an essential parameter to date.

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Silicon Wafer Contouring - High Precision Ring Shape

      With the rapid introduction of 300mm silicon wafers and the
development of larger VLSI chips, the edge shape of wafers appears to
be an essential parameter to date.

As a matter of fact, VLSI chips having an area of 2 to 3 centimeter
square, many of them are located in the wafer periphery and the
product yield is strongly impacted if these chips are failed.  In
addition, as the most of handling operations is made automatically
(the 300mm wafers are too heavy for vacuum wands : around 130 grams
versus 28 grams for 150mm wafers), it is necessary to have adapted
and precise edge rims.

      Present shape (Fig. 1):

                            (Image Omitted)

Fig. 1 shows the standard shape that was introduced in the market,
more than 20 years ago, which has been currently used so far.  It has
two main advantages: it significantly reduces edge chipping and it
prevents photoresist buildup.

However this shape is not ideal for automatic handling and
particularly if we need to hold the wafer by the rim.  Moreover, the
wafer edge is not a barrier against contamination particles that may
come from the periphery.  Finally, the active area is not well
defined since we do not see well when the edge drop starts.  This
last point is a concern for new structures such as SOI (Silicon On
Insulator) wafers that presently appear with significant volumes in
the market.

      High precision rin...