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Z-FET scheme for high-mobilty FinFET CMOS Disclosure Number: IPCOM000123018D
Original Publication Date: 2005-Apr-04
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 34K

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Z-FET scheme for high-mobilty FinFET CMOS

Achieving dual-plane high-mobility with effective layout density has previously required the chevron technique. This technique has two drawbacks, 1. it requires Sidwall Image Transfer (SIT), and 2. it requires packing 22.5 degree oriented fins which is difficult for physical design migration. We provide a simpler solution by using 45-degree pfet fins with two conventional fin masks and fin height adjusted to provide adequate pfet current density. We (optionally) make use of the prior-art reduced-fin-height technique to provide finer drive tuning for nFETs.

Four key elements comprise this technology:
1. pFET fins at +/- 45 degrees on {110} planes
2. Hfin adjusted to compensate density of pFETs
3. Lgate on pFET is selectively compensated shorter
4. SRAMs use 0 degree pFETs.

In Figure 1 an overview of the design point for a CMOS inverter is described.


Design Point:

Tfin = 35nm
Tox = 0.9nm
Hfin = 65nm
FinPitch=80nm (F1, F2 masks + RC)

Use CMOS 11S0 wafer type with notch moved 45 degrees

Use 11S0 PC lithography for Fin

- Three masks define level

      -RC (blocks of silicon) -F1, F2 for dense fin pitch - Vt set by halo (low, regular, high) - DG available as per planar process

Mask to strip fin hard mask on RC blocks for passives


100% Manufacturing-Proven Processes


Figure 1: ZFET CMOS inverter.

A process flow for this technology is outlined in Fig. 2. An SOI or bulk starting wafer can be used, however an SOI...