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Controlled Gold Dissolution Bump Structure for Low Cost Flip Chip Joining

IP.com Disclosure Number: IPCOM000123040D
Original Publication Date: 1998-Apr-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Shohji, I: AUTHOR [+1]

Abstract

Disclosed is a bump structure for low cost flip chip joining on the epoxy base substrate. This structure can make a flip chip joining by reflow soldering without special treatment for the pad surface of substrate.

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Controlled Gold Dissolution Bump Structure for Low Cost Flip Chip
Joining

        Disclosed is a bump structure for low cost flip chip joining
on the epoxy base substrate.  This structure can make a flip chip
joining by reflow soldering without special treatment for the pad
surface of substrate.

  Our bump structure is shown in Figure 1.  Two layers are existed
on the Al pad of LSI (Large Scale Integrated) chip.  This stacked
layer is formed by plating, CVD (Chemical Vapor Deposition) method
and so on.  On reflow soldering, Au is not melted and In layer is
only melted.  The LSI (Large Scale Integrated) chip, which have bumps
as shown in Figure 1, is placed on the substrate pads and reflowed in
order to make a flip chip joint in Figure 2.  After reflow soldering,
Au-In compound layer is formed on the boundary between Au layer and
In layer.  The growth rate of Au-In compound is slower than that of
Au-Sn compound so that the dissolution of Au into solder layer can be
prevented.  Therefore, this In-base flip chip joint comes to be
higher reliability than Sn-base one.

  Even solders like In-3Ag,In-48Sn and In-40Sn-20Pb(weight %), which
react Au and form Au-In compound, are possible for the material of
solder layer as shown in Figure 1.  The thickness of Au bump layer
and In (solder) bump layer are necessary to be over 30 and 15 micron
meter respectively in case of joining by reflow soldering.  This bump
structure enable us to be also applied for the thermocompr...