Browse Prior Art Database

Built-in Self Test Circuit with PLL(Phase-Locked Loop) Circuit

IP.com Disclosure Number: IPCOM000123120D
Original Publication Date: 1998-May-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Authors:
Mori, Y Miyatake, H Tanaka, M

Abstract

Disclosed is a built-in self test (BIST) circuit which has a phase-locked loop (PLL) circuit as a clock signal generator, and is embedded in an integrated circuit (IC) chip for testing a circuit block or all of the circuits in the IC. The BIST with PLL enables high-speed testing of on-chip circuit blocks such as memory macros even when the clock supplied by an external tester such as an LSI (Large Scale Integration) tester is not fast enough for the functional and AC(performance) testing of the circuit blocks.