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Browse Prior Art Database

Over-Erase Screen Method

IP.com Disclosure Number: IPCOM000123144D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Ichinose, M: AUTHOR [+2]

Abstract

Disclosed is a test method of flash memory chips to sort out bad ones that will be over-erased and do not function after repetition of program and erase operations. Once over-erase occurs in erase operation, chips do not function correctly in program or erase verifications or read operation. Generally, it is impossible to predict when it will occur. The test method can detect this kind of chip easily in wafer test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 77% of the total text.

Over-Erase Screen Method

   Disclosed is a test method of flash memory chips to sort
out bad ones that will be over-erased and do not function after
repetition of program and erase operations.  Once over-erase occurs
in erase operation, chips do not function correctly in program or
erase verifications or read operation.  Generally, it is impossible
to predict when it will occur.  The test method can detect this kind
of chip easily in wafer test.

   In flash memory chips, internal circuitries define internal
program and erase verification levels.  The test method first
measures both of them and defines new ones based on them to program
and erase cells deeply.  Then, program and erase operations are
repeated with those reference levels.

   The following table is an example flowchart of the test
method.
  1.  Step1.  Measure Both Internal Program and Erase
               Verification Levels
  2.  Step2.  Program Data 0 Verify at (Internal Program
               Verification Level) -0.20V
  3.  Step3.  Erase Data Verify at (Internal Erase
               Verification Level) +0.25V
  4.  Step4.  Read Data 1 Read at (Internal Erase Verification
               Level) +0.20V
  5.  Step5.  Program Data 0 Verify at (Internal Program
               Verification Level)

   Generally, chips that are programmed deeply need long erase
pulse to erase data completely.  On the other hand, the high...