SRAM Cycle Time Test Procedure

SRAM Cycle Time Test Procedure

   An SRAM cycle time test is defined to allow testing of
very fast array cycle times, in the presence of array built-in
self-test (ABIST) circuitry having relatively slower cycle times.
The test takes advantage of the fact that the array data outputs come
from L1 latches within scannable shift register latches (SRLs).

   Like typical L1 latches, the array output latches have two
input data ports - a system data port and an LSSD scan port.  The
system data port is driven by a sense amp within the array and is
clocked by a derivative of the array clock, while the scan port is
driven by the L2 latch of the preceding SRL in the scan chain and is
clocked is by the LSSD A clock.  By initializing the array and the
scan chain such that these two data ports receive data of opposite
logic states, the array's cycle time can then be tested with a simple
clock sequence, as follows in Fig. 1:

                            (Image Omitted)

   Assuming the array and scan chain are initialized with
logical 0 and 1, respectively, then the above clock sequence will
first load a 0 into the array output latch (first array clock),
followed by a by a 1 (A clock) and another 0 (second array clock).
For manufacturing testing, Tcycle is set at the array's required
minimum cycle time, and a failure is detected when the array output
latch is observed to contain a 1 rather than a 0, after the second
array clock pulse is applied - the 1 indicates the output...