Method for facilitating hardware debug of an LSSD chip
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Disclosed is a methodology to assist in bringup and debug of an LSSD chip. It requires no extra chip design effort or additional logic. The implementation uses a minimal amount of card logic and system software to examine the state of every latch in the chip at the time of failure.