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Integrated ECC Dynamic RAM With Periodic Refresh Disclosure Number: IPCOM000124271D
Original Publication Date: 2005-Apr-13
Included in the Prior Art Database: 2005-Apr-13
Document File: 1 page(s) / 21K

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This paper describes a technique for embedding the ECC circuitry with the periodic refresh of a dynamic RAM. This provides device encapsulation and reduction of I/O driver circuitry, and lower power.

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Integrated ECC Dynamic RAM With Periodic Refresh

This document describes a low cost mechanism for ensuring ECC-checked/repaired dynamic memory using dynamic refresh cycle. Dynamic memory is essentially a bank of capacitors that gets refreshed periodically (read and written). Various environmental factors (e.g., electrostatic discharge) can cause the small capacitors to register bit-errors. These errors are traditionally detected and accounted for using Error Correction Codes (ECC) such as parity checking. The ECC circuitry is normally off-board of the memory system (e.g, in a data bus/address bus driver level). This means that the ECC circuitry operates when the specific location in the dynamic memory is read out to be transmitted over the data bus or address bus.

The natural processes that create bit errors (such as ESD) are stochastic and time-sensitive -- the probability of an additional bit error increases by duration. Given this, the long delays between reads of a specific memory location can increase the probability of multiple bit errors within the memory frame, causing more errors to be found than can be handled by the ECC circuitry or require more expensive ECC circuity to handle the additional bit errors.

Dynamic memory relies on a refresh cycle to systematically read the contents of each bit and write it back into the memory cell. This refreshes the charge within the capacitors. Instead of waiting for a CPU-driven I/O operation before checking for bit ...