Browse Prior Art Database

(Leakage #7) Pulse Gated Keeper for Dynamic Logic Disclosure Number: IPCOM000124552D
Original Publication Date: 2005-Apr-27
Included in the Prior Art Database: 2005-Apr-27
Document File: 4 page(s) / 71K

Publishing Venue



A two-phase dynamic logic keeper circuit and methodology having a second keeper device which is gated by a pulse that arrives slightly ahead of the evaluation signal, the pulsed signal turns off the gated keeper device during logic evaluation; hence, preventing the gated keeper from supplying current to the keeper device during evalation, thereby enhancing performace of the pull-down logic evaluation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 4

(Leakage #7) Pulse Gated Keeper for Dynamic Logic

The feedback keeper device is used to maintain data until the dynamic logic circuit is pre-charged. When the evaluation signal is asserted high the logic/data stack is evaluated. When the logic is evaluated in traditional circuits the pull-down stack must overcome the current provided by the keeper device, reducing performance and increasing power.

The Diagram 1 shows a typical dynamic circuit design. P1 is the pre-charge device. When PCHARGEN is low the device is on and restores the internal node to a logical one. When PCHARGEN is HIGH, the keeper device P0, maintains the logical one until the pull-down stack is evaluated. The DATA inputs represent various data values. The EVAL represents a clocked evaluation signal. When EVAL is active high the DATA state in that portion of the pull-down stack is evaluated. If the DATA is also high then the internal node is pulled down (in opposition to the current supplied by the keeper device shown in Diagram
2), forcing Z to a logical one. If the DATA is low then the internal node is not pulled down and Z remains at a logical zero.

Diagram 1- Typical dynamic design

Diagram 2-Pull-Down Stack


[This page contains 1 picture or other non-text object]

Page 2 of 4

Diagram 3- Typical Timing Diagram

This concept proposes adding a second device to the keeper stack. This device should be controlled by a gating pulse that arrives slightly ahead of the evaluation signal. When the gating...