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Various Configurations of Chip Multiprocessor (CMP), System on a Chip (SOC), and Multi-core (MC) Integration Disclosure Number: IPCOM000124954D
Publication Date: 2005-May-13

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Various Configurations of Chip Multiprocessor (CMP), System on a Chip (SOC),

and Multi-core (MC) Integration

May 2005

1           About this document

                    This document presents and discusses various configurations of CMP (Chip Multiprocessor) and SOC (System on a Chip) chips.  In particular, the document discusses integration of components into CMP and SOC chips and into packages containing systems with a CMP and/or SOC chip or chips.  A CMP system is a system including at least one CMP chip.  A SOC system is a system including at least one SOC chip.

                    A processor is an electronic component that executes instructions.  Some processors are general purpose processors.  Other processors are specialized processors.  A core may be thought of as a unit of replication.  A core could contain one processor, more than one processors, no processors, or part of a processor, or parts of more than one processor.

                    In CMP and SOC chips, more components are placed on a chip (also called an integrated circuit and a die) than a single computer processing element, or a general purpose central processing unit (CPU).  More than one core may be placed on the same chip (making a multicore CMP) or in a SOC chip (making a multicore SOC chip).  The same chip may be both a CMP and a SOC chip.  It is expected that many SOC chips will also be CMP chips.  Multicore chips have been introduced and it is expected that many, if not most, processors in the future will be multicore processors.  Integration of components may also be done in a package including more than a single chip, where at least one of the chips is a CMP, SOC or combined CMP and SOC chip.  To keep the following discussion simpler, unless it is made clear to the contrary, the examples discussed below may be in a CMP chip, an SOC chip, a combined CMP and SOC chip, with or without multiple cores, and in an associated CMP system or SOC system.  Further, any of the chips discussed may be put in a package by itself or with other chips or components.

2           Table of Contents

1.                 About this document

2.                 Table of Contents

3.                 Preliminaries

                    3.1               Integration

                    3.2               Configurations

                                        3.2.1            Recursive Compositions of Configurations

4.                 Integration of separate pieces

                    4.1               Disconnected integration

                    4.2               Criteria for integrating sub-graphs of a computer system

5.                 Basic Processor Architecture

6.                 CMP Cache Configurations

                    6.1               The Case of Three of More Levels of Cache in a CMP System

                    6.2               Alternate Configurations

7.                 Physical Layout Considerations for CMPs

8.                 Conclusion

3           Preliminaries