Method, apparatus and HDL for implementing variable delay in cycle simulation.
Original Publication Date: 2005-Jun-03
Included in the Prior Art Database: 2005-Jun-03
This article provides a generic means of efficiently generating a variable delay in a cycle based simulation engine. A basic circuit is described that can easily be implemented in Hardware Definition Language such as Verilog HDL.
Method, apparatus and HDL for implementing variable delay in cycle simulation .
All cycle simulation engines have the ability to generate a two cycle delay clock , this article uses this two cycle delay clock (referred to as dly_clock in all subsequent diagrams) along with a user configurable input to implement variable delay.
The logic in this article uses a pair of counters and paired control signals on both the positive and negative edges of the dly_clock to model delays with an accuracy of one cycle.
The two counters represent a single decrementing value, but instead of decrementing from itself at a dly_clock edge they decrement from their counterpart that operates on the opposite edge of dly_clock. Thus the counter value is decremented once per cycle.
The count down sequence is started by the edge that first detects that the output is not the same as the input.
At the end of the count down sequence the output is toggled to match the input, thus producing a variable delayed output.
The full circuit is illustrated in the full_circuit.gif diagram shown below.
There are five main parts to this circuit.
1. The final output is selected by a simple delay_select mux output at the end of the logic, based upon the delay configuration it selects from the trivial 0 delay case, the 1 cycle delay case and the 2 or more cycle delay case.
2. The minimal turnaround for the complex counter logic is 2 cycles so the 1 cycle delay case is accomplished by capturing the input on both positive and negative edges, then based upon these outputs a...