Browse Prior Art Database

Flexible ID Mechanism for Test and Set Semaphore Disclosure Number: IPCOM000125494D
Original Publication Date: 2005-Jun-03
Included in the Prior Art Database: 2005-Jun-03
Document File: 1 page(s) / 22K

Publishing Venue



SoC implementation of integrated circuits has the potential to reduce system development costs, power, size and improve reliability. Existing SoC implementations are based on uniprocessor platforms. However, there is a growing trends towards SoC implementations of IC using multiprocessor platforms. Product differentiation is becoming a competitive advantage. Users are increasingly adopting processor customization techniques such as ISA extensions and configurable processor technology, leading to heterogeneous multiprocessor platforms with independently optimized CPUs. Multicore and multiprocessor SoC systems typically use tightly coupled software programs and processes running in independent peer processors. These independent execution units must be able to communicate with one another in a timely manner. Current art usually uses mailboxes with atomic Test-and-Set (tns) semaphore mechanisms to implement inter-process communication (IPC) protocols between processes and processors. In dynamic, real-time embedded SoC devices, processes and processors must be reactive to external stimulus and adjust execution priorities appropriately. Discovery of undue latency on atomic inter-processor messages using tns is a key part of tuning the system at run-time. We propose an extension to current art tns atomic semaphores by providing a transparent method of ID tagging acquisition or request of the semaphore in hardware. Tns hardware automatically captures the ID of the processor or process which is either the owner or the requester. Operating system software uses the ID tag to determine how long a process owns the semaphore, or how long a process is waiting for the semaphore. Discovering semaphore latency allows the operating system to dynamically adjust process execution priorities to balance latency according to the current SoC workload.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 1

Flexible ID Mechanism for Test and Set Semaphore

The concept of semaphore is an old idea. It can be implemented purely in software, as a mix of hardware and software, and as pure hardware. This invention deals with the pure hardware version. Historically, a pure hardware version is a single bit of data with three operations on it (from the bit's point of view). These operations are read, write-to-a-one, and write-to-a-zero, also known as test, set and clear, respectively. In its use, from a program's point of view, there are only two operations : test & set (tns), and clear. The two portions of the tns operation must be performed atomically, meaning no operation on the bit may occur in-between the test an the set part of a tns operation. The nature of a semaphore is that multiple processes running on multiple processors need to access it. This implies the semaphore hardware is sitting out on a bus structure of some sort that the processors share, so that all processors may access the semaphore. Many such bus structures provide for atomic operation which could be used to implement a read bus cycle (to test the semaphore) and a write bus cycle ( to set it ), but many bus structures do not. For this reason, the tns operation is frequently implemented as a read bus cycle, and the hardware which contains the semaphore bit knows that when that bit is read, it must also be set with no intervening read or clear operation. This must be a read cycle on the bus, because data must be returned to the process so that the process may test if the semaphore is set or not. Frequently, the clear operation is a write operation.

A semaphore with only these read and write bus operations is sufficient to satisfy the requirements of resource sharing among processors. This invention is an extension to these simple tns and clear operations to enable more information to be stored in the semaphore to facilitate maturing needs. Two possible uses of these extensions are for debug purposes and for tuning purposes. The immediate problem is that the most important operation on the semaphore, which is the tns instruction, goes across the system bus as a...