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Method to Detect Disconnects during Simulation of an SOC-based Design Disclosure Number: IPCOM000125697D
Original Publication Date: 2005-Jun-13
Included in the Prior Art Database: 2005-Jun-13
Document File: 4 page(s) / 34K

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Disclosed is a solution for detecting disconnects, or other states during the simulation of a System-On-Chip design, given a set of user defined conditions..

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Method to Detect Disconnects during Simulation of an SOC -based Design

System-on-Chip (SOC) designs are becoming increasingly complex with multiple bus architectures supporting a sizeable variety of cores and processors. Integration using existing and potentially novel Intellectual Property (IP) cores is common in the development of an SOC. The integration, or "stitch", is typically done manually in a Hardware Description Language (HDL), instantiating several levels of a hierarchical design. The integration of the "stitched" cores is then verified using a testbench, which through compilation detects primarily syntax errors, and simulation, where testcases help detect real-world scenario problems. Time-to-market pressures of SOC's require that testbench bringup be expedited, so that preliminary simulation results can increase confidence of the design as other stages of the SOC process (e.g. synthesis, timing) continue.

A significant amount of simulation time is spent debugging disconnects which invariably arise due to human error in the top level integration. These include, but are not limited to, signals that are disconnected due to transposition errors, case errors, spelling errors and incorrect specification of bus widths. The disconnects are important to track and correct since they prevent proper simulation of the cores, which in turn hinders the full simulation of the SOC. This invention detects such disconnects early during the simulation process.

Currently, the existing method to detect such disconnects is to dump the appropriate levels of hierarchy of the design using an HDL simulator (e.g. NC-Verilog*, MTI Modelsim**) in waveform output. The waveforms are then observed in a simulator or other vendor supplied waveform viewer (e.g. Debussy***), where the Verification Engineer laboriously selects and views all the appropriate Input and Output signals to and from the "stitched" cores at the top level of integration. The disconnects, represented in the waveform viewers as high "Z" (high impedance), are then traced back in the integration file where the port connections between the top-level modules are scrutinized for the aforementioned errors. To dump and trace all Input and Output signals associated with each core in the top level "stitch" in a waveform viewer is a tedious task, prone to human error and can be prohibitive on very large designs.

Other methods are at different stages of the SOC process. During the design process of individual cores that comprise the SOC, a syntax checker (e.g. verilint for Verilog) can detect syntax errors. The problem is that it is typically not applied to the fully "stitched" SOC file. A drawback of syntax checkers is that they do not perform any simulation of the design, where the high "Z" state representing a disconnect may be flushed out or reappear after a set time or event (e.g. reset).

Similarly, the synthesis process, which typically starts after some simulation has been conducted, ca...