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InfiniBand Host Channel Adapter Interrupt Timers and Summaries Disclosure Number: IPCOM000126453D
Original Publication Date: 2005-Jul-18
Included in the Prior Art Database: 2005-Jul-18
Document File: 2 page(s) / 56K

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A method to reduce the number of hardware interrupts generated using time stamps and summary bytes is described. Reducing the number of interrupts facilitates scaling to many I/O hubs and bridges and many processors. If events are being retrieved adequately by the firmware/software using polling, no interrupts are generated. If the hardware perceives that events are not being serviced by the firmware/software, an interrupt is generated. Summary bytes are provided in system memory to improve the efficiency of polling, thus reducing the number of interrupts.

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InfiniBand Host Channel Adapter Interrupt Timers and Summaries

    Rather than using active timers, each Event Queue (EQ) context contains a next interrupt delay value and a next interrupt time stamp. The adapter has a local time register that has no particular relationship to the actual Time of Day (TOD).

    Each EQ also needs to know if there are any completion events on the queue. This is implemented with an up/down counter (the completion event counter - CEC) that keeps track of the number of EQ Pending bits in the associated completion queues (CQs) that are set to one. Each time the adapter puts a completion event on the EQ, it sets the EQ Pending bit for the CQ, examines the value of the CEC to see it is empty, and increments the CEC by one. Each time the adapter driver logically removes a completion event from the EQ by resetting the EQ Pending bit in the CQ, the adapter decrements the CEC by one. When the CEC is equal to zero, the EQ has no completion events on it; it is empty of completion events.

    The table shows the actions taken each time a completion event is put on the EQ. The top shows the EQ empty of completion events state, and the left shows the relationship between the current local time and the Next Interrupt Time Stamp. In all cases, the EQ entry (EQE) is always stored and a Secondary Summary Byte is written if enabled, the CEC register is incremented by 1. If the EQ is empty of completion events, the adapter sets the Primary Summary Byte as specified by the EQ Controls. The adapter then adds the Next Interrupt Delay value to the current local time, and sets this time stamp (the Next Interrupt Time Stamp). If the PSUM+INT bit is set to one, a hardware interrupt is also generated after all of the required writes to main memory have completed. Nothing more happens until the next completion event is put on the EQ.

    If the EQ is not empty of completion events when the adapter puts a completion event on the EQ, the adapter compares the Next Interrupt Time Stamp to the current local time. If the current local time is ahead of (later in time) the Next Interrupt Time Stamp, the adapter assumes that the adapter driver is not being responsive. It sets the Next Interrupt Time Stamp, and generates a hardware interrupt. If the current l...