Browse Prior Art Database

Structures for Electromigration Testing with Stacked Vias Disclosure Number: IPCOM000127311D
Original Publication Date: 2005-Aug-22
Included in the Prior Art Database: 2005-Aug-22
Document File: 6 page(s) / 122K

Publishing Venue



We are proposing that stacked vias be used in the design of electromigration structures. This would allow one to determine the effect of via strain on the electromigration lifetime. Also, the proposed structures can be thermal cycled and then electromigration tested to see if cracks formed during the initial stress affect the electromigration performance. It is worth mentioning that existing macros are not constructed in a way that utilizes strain in stacked vias as a test condition for electromigration structures. While electromigration macros do not possess stacked vias in low-k dielectrics that are pinned between SiO2 layers, stacked via macros that are pinned have links at the metal levels that are too short for appropriate electromigration testing.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 34% of the total text.

Page 1 of 6

Structures for Electromigration Testing with Stacked Vias

Failure due to electromigration and thermal cycle have been reported for aluminum (Al) and copper (Cu) metallization. Electromigration is a failure mechanism for metal interconnects in which metal atoms migrate in the direction of the electron flow. The migration of conductor atoms leads to void formation at the cathode end of the line, and eventually causes the resistance of the structure to increase. Typically, electromigration testing occurs on two-level structures, where a diffusion barrier is located at the cathode end of the structure to prevent material migration from the lower level metal into the upper level metal. Figure 1 shows an electromigration structure, where a tungsten (W) stud at the cathode end is in contact with a multilayered Al interconnect. The W stud is an ideal diffusion barrier, which allows void formation directly above the W stud in the Al interconnect. Other materials also act as diffusion barriers, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN). Figure 2 shows another type of electromigration structure in which W studs are located at both the cathode and anode ends of the interconnect. Reliability under thermal cycle conditions is one of the main concerns when integrating BEOL structures with low dielectric constant dielectrics. The cause of thermal cycle fails is the mismatch in the thermal expansion coefficient (CTE) between the metallization and the surrounding insulator. For example, the CTE of Cu is appoximately 16 ppm/oC while that of SiLK is approximately 60 ppm/oC. As a result, the Cu metallization is strained during thermal cycle testing, which can lead to crack formation in Cu vias and eventual failure. Stacked vias appear to be the most susceptible structures to thermal cycle failure, especially when rigid silicon dioxide (SiO2) layers are located above and below the metallization. A typical stacked via structure used for thermal cycle study is shown in Figure 3, which consists of two levels of SiLK (M1/CA, M2/V1) followed by two SiO2 levels.

While the thermal cycle performance of a given process can be evaluated by stressing specifically designed test structures, is is unknown how the strain generated in the stacked vias will affect the electromigration lifetime. Given the importance of thermal cycle failure for Cu metallization and low-k dielectric materials, it would be beneficial to understand how thermal cycle stress and via strain affect the electromigration lifetime. Therefore, it is highly desirable to have a structure that causes a large strain in the region where electromigration failure occurs. We have identified a stacked via design that is primarily intended to evaluate the effect of via strain on electromigration failure in Cu Dual Damascene structures. A recently filed invention, IBM Docket No. YOR9-2004-0056, discloses the design of stacked via structures for the purpose of the...