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Method to Improve Functional Verification of a Design with Two or More Sub-units Disclosure Number: IPCOM000129240D
Original Publication Date: 2005-Oct-03
Included in the Prior Art Database: 2005-Oct-03
Document File: 2 page(s) / 24K

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The proposed method of functional verification provides an improvement over the conventional method in the area of efficiency and accuracy through the reuse of code as both a driver and a checker. This will eliminate the need for two separate pieces of code almost halving the verification design and maintenance effort.

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Method to Improve Functional Verification of a Design with Two or More Sub -units

The conventional method of functional verification of a logic unit with 2 or more sub-units ( or of 2 designs or more ) usually involves verifying each of the sub-units independently along with verifying the whole unit. To functionally verify a logic unit, the usual simulator requirement includes a design under test (DUT), a driver to irritate the DUT, an interface checker to check signal protocol and a DUT checker to check for correct response. The driver, the interface checker, and the DUT checker are usually developed independently of each other. The drawback to this method of simulator development for functional verification is that it is inefficient and inaccurate. Using the conventional method requires a large amount of time and manpower to develop the simulator and ensure the accuracy of the simulator.

The proposed method will increase the efficiency and accuracy by using the driver for one of the DUTs as the checker for the other DUT. Even though they are one entity, they still behave distinctly as a driver and a checker in their respective environments. Consider a simple design which is made up of design A and design B, two units which interact with each other. Using the conventional method and not counting interface checkers, 2 driver and 2 checkers are needed to verify the designs. This means four distinct pieces of code. Whereas, with the proposed method, only 2 functional verification stimulators (FVS A,B) are needed to verify the same design. For design A, FVS B would be used as the stimulus/behavioral and FVS A would check design A. For design B, FVS A would be used as the stimulus/behavioral and FVS B would check design B...